1. Field of the Invention
The invention relates to a data transaction mechanism that prevents transaction collisions on a bus, and more particularly to a data transaction mechanism that prevents transaction collisions on a System Management Bus (SM Bus) and/or an Inter-Integrated Circuit (I2C) bus.
2. Description of the Related Art
A System Management Bus (SM Bus) and an Inter-Integrated Circuit (I2C) bus are interfaces to connect important devices within a system. The SM Bus and the I2C bus have two bidirectional lines used for communication between devices, which includes a serial data line for transferring a data signal, and a serial clock line for transferring a clock signal. Although the SM Bus and the I2C bus are defined by different specifications, they follow the same transmission protocol. Generally, when there is no data to be transferred, signals on both the data and clock lines of the SM Bus and the I2C bus are kept at a high level. When transaction occurs, a high-to-low level or low-to-high level transition on the data line is only allowed when the clock signal is at high level.
For a multiple-master supported system, because any device, regardless of whether it's a master or slave device, that has to transfer data via the SM Bus and the I2C bus needs to be connected to the SM Bus and the I2C bus, a transaction by multiple master devices being connected to the same bus may be triggered. Specifically, when there is more than one master device issuing a message to trigger a transaction at about the same time, collision occurs, since master devices are unable to detect transaction requirements of other devices. As such, detection of transaction collision by the SM Bus and the I2C bus has been developed.
FIG. 1 shows the waveforms of the signals on the data line and clock line of an SM bus and on the data lines of two master devices that are connected to the SM bus. As shown in FIG. 1, DATA 1 represents the data line of a first master device, DATA 2 represents the data line of a second master device, SDA represents the data line of the SM bus, and the SCL represents the clock line of the SM bus. According to the mechanism defined by the specification of SM bus, one master device may determine whether it wins the arbitration of the SM bus according to the signal level on the data line. When the clock signal is at a high level and the data signal of the master device is at a low level, the master device determines that it wins the arbitration of the SM bus. As shown in FIG. 1, the first master device and the second master device continuously monitors the signal levels on the data lines during the first clock period CK1, the second clock period CK2, the third clock period CK3, . . . etc. In the example, the first master clock finally observes that it has lost the arbitration at the third clock CK3 since the signal level of the data line is different than what was expected (as shown in the figure, the clock signal is at a high level and the data signal of the master device is at a high level).
However, for such arbitration mechanisms, data error occurs when the master device is not capable of dealing with the transaction collision. As shown in FIG. 1, during the third clock period CK3, since the data signal of the second master device is at a low level when the clock is at a high level, the second master device wins the arbitration. Specifically, since data signal of the first master device is at a high level when the clock is at a high level, the first master device loses the arbitration. However, the high level on the data line DATA 1 after the third clock CK3 may refer to a valid data transfer, instead of a stop phase of a data transaction. That is, when the second master wins the arbitration, the data transaction of the first master device may have not yet been finished. Once the first master device can not handle the transaction collision, data error may occur at the first master device, which may further cause serious system problems.
Thus, a novel data transaction mechanism that prevents transaction collisions on the SM bus or the I2C bus is highly required.